The present invention relates to a standard cell formed on a semiconductor substrate, a standard cell array formed on a semiconductor substrate, and a system and a method for placing and routing standard cells.
As a layout design technology for realizing a LSI (large scale integrated circuit) on a semiconductor substrate with a high integration density for a short period of time, a standard cell type LSI design technology is widely utilized, in which small unitary circuits such as an inverter and an NAND gate are previously prepared as standard cells, and those standard cells are placed in the form of an array and interconnected to form an LSI.
Referring to FIG. 18A, a layout diagram of a standard cell type LSI is illustrated. A plurality of cell arrays are placed, each of the cell arrays being formed of a plurality of function cells 106 having the same width (height in the drawing) and placed in the form of an array. A routing channel 1801 is reserved between each pair of adjacent cell arrays. In the routing channel 1801, there are located an inter-cell connection 1802 for interconnecting between cells included in the same cell array, and an inter-array connection 1803 for interconnecting between cells which are included in different cell arrays, respectively.
Referring to FIG. 18B, there is shown a pattern diagram of the inside of one typical prior art standard cell. The shown standard cell is a function cell 106a having an inverter function. In FIG. 18B, the reference number 111 designates an N-well, and the reference number 112 indicates a P-type diffused layer. The reference number 113 shows an N-type diffused layer, and the reference number 114 denotes a polysilicon. The reference number 115 designates a contact hole between the P-type or N-type diffused layer and a first level metal. The reference number 116 indicates a contact hole between the polysilicon and the first level metal. The reference number 117 shows the first level metal. The reference number 120 denotes a VDD power supply line formed of the first level metal. The reference number 121 designates a VSS power supply line formed of the first level metal. In the N-well 111, a P-channel MOS transistor having a source and a drain formed of the P-type diffused layer 112 is formed. In a P-type substrate region at the outside of the N-well, an N-channel MOS transistor having a source and a drain formed of the N-type diffused layer 113 is formed.
In the prior art standard cell, all the cells have the same constant width (height in FIG. 18B), and the VDD power supply line 120 and the VSS power supply line 121 having the same fixed width are located at an upper end portion and at a lower end portion of the cell, respectively, as shown in FIG. 18B. An area between the pair of power supply lines in the cell is used to form the transistors included in the cell and to locate interconnections between terminals (contacts) within the cell (called an xe2x80x9cin-cell wiringxe2x80x9d in this specification). On the other hand, the routing channel has to be used for the interconnection between cells. However, the width of the cell is determined to meet a function cell such as a flipflop which needs a number of transistors and a complicated in-cell wiring. Therefore, the following problem has been encountered in the prior art standard cell. In a relatively simple function cell such as an inverter and a 2-input NAND gate which has a simple in-cell wiring, although there arise many empty areas for the first level metal, the empty areas could not be utilized for the inter-cell connection. In addition, the power supply lines extending through all the standard cells have the constant width, and it is not so easy to change the width of the power supply lines in accordance with the magnitude of a required power supply current.
Under this situation, Japanese Patent Application Pre-examination Publication No. JP-A-06-169016 discloses a standard cell having an empty area which is provided between a power supply line and an in-cell wiring area and which can be utilized for the inter-cell connection. Referring to FIG. 19A, there is shown a wiring area diagram of a standard cell in accordance with this second prior art. An empty area 123 is provided between the VDD line 120 of the first level metal and an in-cell wiring area 122, and another empty area 124 is provided between the VSS line 121 of the first level metal and the in-cell wiring area 122. These empty areas 123 and 124 can be utilized for the inter-cell connection so as to realize an elevated integration density.
In addition, Japanese Patent Application Pre-examination Publication No. JP-A-03-062551 discloses a standard cell having a device formation area extending into an outside of the power supply line. Referring to FIG. 19B, there is shown a wiring area diagram of a standard cell in accordance with this third prior art. An in-cell wiring area 122 is provided between the VDD line 120 and the VSS line 121, similarly to the first prior art example shown in FIG. 18B. However, a device formation area 125 depicted by a chain line extends into an outside of each power supply line. Since this outside area can be utilized as a wiring area, the outside area can be utilized for the inter-cell connection. In addition, even if the position of the power supply lines is standardized for all the cells, it is possible to freely set a substantial cell width determined by the size of the device formation area.
Furthermore, Japanese Patent Application Pre-examination Publication No. JP-A-05-055381 proposes a standard cell having no power supply line pattern. Referring to FIG. 19C, there is shown a wiring area diagram of a standard cell in accordance with this fourth prior art. The standard cell includes only an in-cell wiring area 122 including transistors formed in the cell and a wiring pattern for connecting between terminals in the cell. After a required number of standard cells are placed in the form of an array, a power supply line pattern which has a line width determined on the basis of the length of the cell array and a power consumption, is generated to connect to each standard cells. Therefore, the power supply line can have an optimum line width.
However, the standard cell of the second prior art are difficult to optimize the width of the power supply line, and are restricted to have a constant cell width. The standard cell of the third prior art is difficult to optimize the width of the power supply line. The standard cell of the fourth prior art are restricted to have a constant cell width. In addition, since the device formation area is not used for the inter-cell connection, the wiring density is low.
Accordingly, it is an object of the present invention to provide a standard cell, a standard cell array, and a system and a method for placing and routing standard cells, which have overcome the above mentioned problems of the prior art.
Another object of the present invention is to provide a standard cell, a standard cell array, and a system and a method for placing and routing standard cells, capable of forming an inter-cell connection in an area between a power supply line and an in-cell wiring area and also capable of ensuring the power supply line having an optimum line width, without a restriction requiring a constant cell width.
According to a first aspect of the present invention, there is provided a standard cell comprising a power supply terminal of a diffused layer, an input terminal of a first level metal and an output terminal of the first level metal.
More specifically, the standard cell in accordance with the present invention comprises a function circuit including at least one P-channel transistor and at least one N-channel transistor; a first power supply terminal for supplying a first power supply voltage to the at least one P-channel transistor, a second power supply terminal for supplying a second power supply voltage to the at least one N-channel transistor, and an input terminal and an output terminal for the function circuit. The first power supply terminal is provided at a P-type diffused layer of the at least one P-channel transistor supplied with the first power supply voltage, and the second power supply terminal is provided at an N-type diffused layer of the at least one N-channel transistor supplied with the second power supply voltage. The input terminal of the first level metal and the output terminal of the first level metal constitute the input terminal and the output terminal for the function circuit, respectively.
According to a second aspect of the present invention, there is provided a standard cell array including a plurality of standard cells in accordance with the first aspect of the present invention, said plurality of standard cells being formed on a semiconductor substrate and located in the form of an array. The plurality of standard cells are located in such a manner that respective well boundary lines within the standard cells are aligned on one straight line, and a substrate contact cell for connecting a first power supply voltage and a second power supply voltage to the semiconductor substrate and a well formed in the semiconductor substrate, respectively, is inserted into the standard cell array at predetermined intervals, at least one for a predetermined number of standard cells.
According to a third aspect of the present invention, there is provided a standard cell placement and routing processing system comprising a library file which stores information of various standard cells in accordance with the first aspect of the present invention, a circuit connection information file which stores circuit connection information of an LSI to be developed, a constraint information file which stores constraint information concerning the placement and the routing, a parameter file which stores parameter information including a power supply voltage and an operating frequency of the LSI to be developed and a sheet resistance of the diffused layer, a placement and routing system for executing the placement and the routing of standard cells selected in accordance with the circuit connection information from the circuit connection information file, by utilizing information from the library file, the constraint information file and the parameter file, and an input/output and display apparatus for displaying a history and a result of the placement and the routing and for externally inputting a control command to control the placement and routing system.
According to a fourth aspect of the present invention, there is provided a standard cell placement and routing method for executing a placement and routing of standard cells by using the standard cell placement and routing processing system in accordance with the third aspect of the present invention, the method comprising:
a first step of reading out the circuit connection information from the circuit connection information file;
a second step of reading out from the cell library file, standard cells corresponding to the read-out circuit connection information, and locating the read-out standard cells into a plurality of standard cell arrays, each of the plurality of standard cell arrays including at least one substrate contact cell inserted for every a predetermined number of standards cells, and the standard cells included in each of the plurality of standard cell arrays being arranged in such a manner that respective well boundary lines within the standard cells in each standard cell array are aligned on one straight line in a plan view;
a third step of routing signal lines between the standard cells included in the standard cell array, in accordance with the circuit connection information;
a fourth step of extracting a contour of a wiring area of the signal lines within the standard cell array, and placing a power supply line at the outside of the wiring area;
a fifth step of forming a contact hole at an overlapping portion between the power supply line and the power supply terminal of the diffused layer within the standard cell in the standard cell array, or alternatively, extending a power supply line of the diffused layer from the power supply terminal to the power supply line when the power supply terminal does not overlap the power supply line, and then, forming a contact hole at an overlapping portion between the power supply line and the power supply line of the diffused layer;
a sixth step of discriminating whether or not the resistance of the power supply line of the diffused layer is not greater than a predetermined resistance value stored in the constraint information file;
a seventh step of re-routing the signal lines between the standard cells when it is discriminated in the sixth step that the resistance of the power supply line of the diffused layer is greater than the predetermined resistance value, and then, returning to the fourth step; and
an eighth step of routing a not-connected interconnection in the standard cell array and signal lines between the standard cell arrays when it is discriminated in the sixth step that the resistance of the power supply line of the diffused layer is not greater than the predetermined resistance value.
Specifically, the second step can include:
a first sub-step of reading out from the cell library file, the standard cells corresponding to the read-out circuit connection information, and locating the read-out standard cells into a plurality of standard cell arrays in such a manner that respective well boundary lines within the standard cells in each standard cell array are aligned on one straight line in a plan view;
a second sub-step of inserting the at least one substrate contact cell for every a predetermined number of standards cells in each standard cell array, to complete the plurality of standard cell arrays;
a third sub-step of calculating a power supply line width on the basis of information including the number of the standard cells and the kinds of the standard cells included the standard cell array, the power supply voltage, and the operating frequency;
a fourth sub-step of calculating the width of a routing channel required from the power supply line width, the number of signal lines, and signal paths; and
a fifth sub-step of discriminating whether or not the routing is possible, with reference to a chip size stored in the constraint information file, and returning to the first sub-step when the routing is not possible, and on the other hand, completing the second step when the routing is possible.
Furthermore, the fifth step can include:
a first sub-step of extracting the power supply terminals of the standard cells included in the standard cell array;
a second sub-step of discriminating whether or not the extracted power supply terminal overlaps the power supply line;
a third sub-step of extending the power supply line of the diffused layer from the extracted power supply terminal to the power supply line when the extracted power supply terminal does not overlap the power supply line, so that the power supply line of the diffused layer overlaps the power supply line; and
a fourth sub-step of forming a contact hole at an overlapping portion between the extracted power supply terminal and the power supply line when it is discriminated in the second sub-step that the extracted power supply terminal overlaps the power supply line, or alternatively at an overlapping portion between the power supply line and the power supply line of the diffused layer when it is discriminated in the second sub-step that the extracted power supply terminal does not overlap the power supply line.
In addition, the seventh step can include:
a first sub-step of detecting a signal line which becomes a hindrance in reducing the resistance of the power supply line formed of the diffused layer to not greater than the predetermined resistance value;
a second sub-step of removing the signal line which becomes the hindrance, and providing a through-hole for connecting between the first level metal and a second level metal at an end position to which the removed signal line was connected; and
a third sub-step of discriminating whether or not the resistance of the power supply line formed of the diffused layer shortened as the result of the removal of the signal line is not greater than the predetermined resistance value, and returning to the first sub-step when the resistance is greater than the predetermined resistance value, or alternatively completing the seventh step when the resistance is not greater than the predetermined resistance value.
According to a fifth aspect of the present invention, there is provided a standard cell placement and routing method for executing a placement and routing of standard cells by using a standard cell placement and routing processing system in accordance with the third aspect of the present invention, the method comprising:
a first step of reading out the circuit connection information from the circuit connection information file;
a second step of reading out from the cell library file, standard cells corresponding to the read-out circuit connection information, and provisionally locating the read-out standard cells into a plurality of provisional standard cell arrays;
a third step of dividing the provisional standard cell array into a plurality of cell groups each including not greater than a predetermined number of standard cells which are located adjacent to one another;
a fourth step of selecting one cell group to be processed, from the plurality of cell groups;
a fifth step of routing signal lines between the standard cells within the one selected cell group, in accordance with the circuit connection information from the circuit connection information file;
a sixth step of extracting a contour of a wiring area of the signal lines within the one selected cell group, to register a power supply line inhibit area in the constraint information file;
a seventh step of placing a power supply line along the outside of the power supply line inhibit area within the one selected cell group;
an eighth step of forming a contact hole at an overlapping portion between the power supply line and the power supply terminal of the diffused layer within the standard cell in the one selected cell group, or alternatively, extending a power supply line of the diffused layer from the power supply terminal to the power supply line when the power supply terminal does not overlap the power supply line, and then, forming a contact hole at an overlapping portion between the power supply line and the power supply line of the diffused layer;
a ninth step of discriminating whether or not the resistance of the power supply line of the diffused layer is not greater than a predetermined resistance value stored in the constraint information file;
a tenth step of re-routing the signal lines between the standard cells when it is discriminated in the ninth step that the resistance of the power supply line of the diffused layer is greater than the predetermined resistance value, and then, returning to the fifth step;
an eleventh step of discriminating whether or not the processing for all the cell groups has been completed, when it is discriminated in the ninth step that the resistance of the power supply line of the diffused layer is not greater than the predetermined resistance value, and then, returning to the fourth step when the processing for all the cell groups has not yet been completed;
a twelfth step of replacing the provisional standard cell array composed of the provisionally located standard cells, with corresponding cell groups processed above, when it is discriminated in the eleventh step that the processing for all the cell groups has been completed;
a thirteenth step of interconnecting respective power supply lines of the cell groups processed above to form a power supply line for the standard cell array; and
a fourteenth step of routing a not-connected interconnection in the standard cell array and signal lines between the standard cell arrays.
The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings.